circuit design 筆試題

　　在網(wǎng)上搜到的，應(yīng)該還不是很全吧，歡迎補(bǔ)充:89) 1.please draw the transistor level schematic of a cmos 2 input AND gate and explain which input has faster response for output rising edge.(less delay time)2.please show the CMOS inverter schmatic,layout and its cross sectionwith P-well process.Plot its transfer curve(Vout-Vin) And also explainthe operation region of PMOS and NMOS for each segment of the transfercurve?3.To design a CMOS invertor with balance rise and fall time,please define the ration of channel width of PMOS and NMOS and explain?4.Please draw schematic of a common SRAM cell with 6 transistors,point out which nodes can store data and which node is word linecontrol?5.Please explain how we describe the resistance in semiconductorCompare the resistance of a metal,poly and diffusion in tranditionalCMOS process.

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